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74VHCT373A
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING
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HIGH SPEED: tPD = 6.4 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25C COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.)
SOP
TSSOP
ORDER CODES
PACKAGE SOP TSSOP TUBE 74VHCT373AM T&R 74VHCT373AMTR 74VHCT373ATTR
DESCRIPTION The 74VHCT373A is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input precisely . When the LE is taken low, the Q outputs will be latched PIN CONNECTION AND IEC LOGIC SYMBOLS
precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
June 2001
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INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE Q0 to Q7 D0 to D7 LE GND VCC NAME AND FUNCTION 3 State Output Enable Input (Active LOW) 3-State Outputs Data Inputs Latch Enable Input Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS OE H L L L LE X L H H D X X L H OUTPUT Q Z NO CHANGE* L H
X : Don't Care Z : High Impedance * : Q Outputs are latched at the time when the LE input is taken low logic level.
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
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ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage (see note 1) DC Output Voltage (see note 2) DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 50 -65 to +150 300 Unit V V V V mA mA mA mA C C
ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) Output in OFF State 2) High or Low State
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO VO Top dt/dv Supply Voltage Input Voltage Output Voltage (see note 1) Output Voltage (see note 2) Operating Temperature Input Rise and Fall Time (see note 3) (VCC = 5.0 0.5V) Parameter Value 4.5 to 5.5 0 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 20 Unit V V V V C ns/V
1) Output in OFF State 2) High or Low State 3) VIN from 0.8V to 2V
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74VHCT373A
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 4.5 to 5.5 0 to 5.5 5.5 5.5 0 IO=-50 A IO=-8 mA IO=50 A IO=8 mA VI = VIH or VIL VO = 0V to 5.5 VI = 5.5V or GND VI = VCC or GND One Input at 3.4V, other input at VCC or GND VOUT = 5.5V TA = 25C Min. 2 0.8 4.4 3.94 0.0 0.1 0.36 0.25 0.1 4 1.35 0.5 4.5 4.4 3.8 0.1 0.44 2.5 1.0 40 1.5 5.0 Typ. Max. Value -40 to 85C Min. 2 0.8 4.4 3.7 0.1 0.55 2.5 1.0 40 1.5 5.0 Max. -55 to 125C Min. 2 0.8 Max. V V V V A A A mA A Unit
VIH VIL VOH VOL Ioz
High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Impedance Output Leakege Current Input Leakage Current Quiescent Supply Current Additional Worst Case Supply Current Output Leakage Current
II ICC
ICC
IOPD
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 5.0(*) 5.0(*) 5.0(*) 5.0
(*)
Value TA = 25C Min. Typ. 5.4 6.0 6.4 7.1 Max. 12.3 13.3 8.5 9.5 10.9 11.9 11.2 -40 to 85C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 8.5 1.5 3.5 1.0 1.0 Max. 13.5 14.5 9.5 10.5 12.5 13.5 12.0 -55 to 125C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 8.5 1.5 3.5 1.0 Max. 13.5 14.5 9.5 10.5 12.5 13.5 12.0 ns ns Unit
CL (pF) 15 50 15 50 15 50 50 RL = 1K RL = 1K
tPLH tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ tw ts th tOSLH tOSHL
Propagation Delay Time LE to Q Propagation Delay Time D to Q Output Enable Time Output Disable Time Pulse Width (LE) HIGH Setup Time D to LE HIGH or LOW Hold Time D to LE HIGH or LOW Output to Output Skew time (note 1)
5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*)
6.2 6.9 6.7 6.5 1.5 3.5
ns ns ns ns ns ns
50
(*) Voltage range is 5.0V 0.5V Note 1 : Parameter guaranteed by design. tsoLH = |t pLHm - t pLHn|, t soHL = |tpHLm - tpHLn |
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74VHCT373A
CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter Min. CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) TA = 25C Typ. 4 9 14 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF pF Unit
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Latch)
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 5.0 TA = 25C Min. Typ. 0.6 -0.9 CL = 50 pF 2.0 -0.6 V Max. 0.9 Value -40 to 85C Min. Max. -55 to 125C Min. Max. Unit
VOLP VOLV VIHD
VILD
Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3)
5.0
5.0
0.8
1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
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74VHCT373A
TEST CIRCUIT
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL =15/50pF or equivalent (includes jig and probe capacitance) RL = R1 = 1K or equivalent RT = ZOUT of pulse generator (typically 50)
SWITCH Open VCC GND
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
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WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
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SO-20 MECHANICAL DATA
mm. DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8 (max.) 0.291 0.020 13.00 10.65 0.35 0.23 0.5 45 (typ.) 0.496 0.393 0.050 0.450 0.300 0.050 0.029 0.512 0.419 0.1 TYP MAX. 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. TYP. MAX. 0.104 0.008 0.096 0.019 0.012 inch
PO13L
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TSSOP20 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 6.4 6.2 4.3 6.5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 6.6 6.6 4.48 0.002 0.031 0.007 0.004 0.252 0.244 0.169 0.256 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.260 0.260 0.176 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
0087225C
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com
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